Freescale Semiconductor MCF5329 Reference Manual page 354

FlexBus
transfer start (FB_TS) is asserted.
two clocks of address setup.
FB_CLK
FB_A[23:0]
FB_D[31:X]
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 17-21. Read-Bus Cycle with Two-Clock Address Setup (No Wait States)
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_BE/BWEn
Figure 17-22. Write-Bus Cycle with Two Clock Address Setup (No Wait States)
17-22
Figure 17-21 and
S0 AS
ADDR[23:0]
ADDR[31:X]
S0 AS
FB_CLK
ADDR[31:X]
FB_R/W
FB_TS
FB_OE
FB_TA
MCF5329 Reference Manual, Rev 3
Figure 17-22 show read- and write-bus cycles with
S1 S2 S3
DATA
S1 S2
ADDR[23:0]
DATA
S0
S3 S0
Freescale Semiconductor