Freescale Semiconductor MCF5329 Reference Manual page 628

Synchronous Serial Interface (SSI)
In network mode, data can be transmitted in any time slot. The distinction of network mode is each time
slot is identified with respect to the frame sync (data word time). This time slot identification allows the
option of transmitting data during the time slot by writing to the SSI_TX registers or ignoring the time slot
as determined by the SSI_TMASK register bits. The receiver is treated in the same manner and received
data is only transferred to the receive data register/FIFO if the corresponding time slot is enabled through
SSI_RMASK.
By using the SSI_TMASK and SSI_RMASK registers, software only has to service the SSI during valid
time slots. This eliminates any overhead associated with unused time slots. Refer to
Transmit Time Slot Mask Register (SSI_TMASK),"
Register (SSI_RMASK),"
In two channel mode (SSI_CR[TCH] = 1), the second set of transmit and receive FIFOs and data registers
create two separate channels (for example, left and right channels for a stereo codec). These channels are
completely independent with their own set of interrupts and DMA requests identical to the ones available
for the default channel. In this mode, data is transmitted/received in enabled time slots alternately from/to
FIFO 0 and FIFO 1, starting from FIFO 0. The first data word is taken from FIFO 0 and transmitted in the
first enabled time slot and subsequently, data is loaded from FIFO 1 and FIFO 0 alternately and
transmitted. Similarly, the first received data is sent to FIFO 0 and subsequent data is sent to FIFO 1 and
FIFO 0 alternately. Time slots are selected through the transmit and receive time slot mask registers
(SSI_TMASK and SSI_RMASK).
24.4.1.2.1 Network Mode Transmit
The transmit portion of SSI is enabled when the SSI_CR[SSI_EN and TE] bits are set. However, for
continuous clock when the TE bit is set, the transmitter is enabled only after detection of a new frame sync
(transmission starts from the next frame boundary).
Normal start-up sequence for transmission:
• Write the data to be transmitted to the SSI_TX register. This clears the TDE flag.
• Set the SSI_CR[TE] bit to enable the transmitter on the next word boundary (for continuous clock).
• Enable transmit interrupts.
Alternately, the user may decide not to transmit in a time slot by writing to the SSI_TMASK. The TDE
flag is not cleared, but the SSI_TXD port remains disabled during the time slot. When the frame sync is
detected or generated (continuous clock), the first enabled data word is transferred from the SSI_TX
register to the TXSR and is shifted out (transmitted). When the SSI_TX register is empty, the TDE bit is
set, which causes a transmitter interrupt (if the FIFO is disabled) to be sent if the TIE bit is set. Software
can poll the TDE bit or use interrupts to reload the SSI_TX register with new data for the next time slot.
Failing to reload the SSI_TX register before the TXSR is finished shifting (empty) causes a transmitter
underrun error (the TUE bit is set). If the FIFO is enabled, the TFE flag is set in accordance with the
watermark setting and this flag causes a transmitter interrupt to occur.
Clearing the TE bit disables the transmitter after completion of transmission of the current frame. Setting
the TE bit enables transmission from the next frame. During that time the SSI_TXD port is disabled. The
TE bit should be cleared after the TDE bit is set to ensure that all pending data is transmitted.
24-34
for more information on the SSI_TMASK and SSI_RMASK registers.
MCF5329 Reference Manual, Rev 3
and Section 24.3.19, "SSI Receive Time Slot Mask
Section 24.3.18, "SSI
Freescale Semiconductor