Memory Map/Register Definition - Freescale Semiconductor MCF5329 Reference Manual

Fast Ethernet Controller (FEC)
Signal Name
FEC_TXEN X X
FEC_TXER X — When asserted for one or more clock cycles while FEC_TXEN is also asserted, the PHY sends
19.4

Memory Map/Register Definition

The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The
CSRs control operation modes and extract global status information. The descriptors pass data buffers and
related buffer information between the hardware and software.
Each FEC implementation requires a 1-Kbyte memory map space, which is divided into two sections of
512 bytes each for:
• Control/status registers
• Event/statistic counters held in the MIB block
Table 19-2 defines the top level memory map.
0xFC03_0000 – FC03_01FF
0xFC03_0200 – FC03_02FF
Table 19-3 shows the FEC register memory map.
Address
0xFC03_0004 Interrupt Event Register (EIR)
0xFC03_0008 Interrupt Mask Register (EIMR)
0xFC03_0010 Receive Descriptor Active Register (RDAR)
0xFC03_0014 Transmit Descriptor Active Register (TDAR)
0xFC03_0024 Ethernet Control Register (ECR)
0xFC03_0040 MII Management Frame Register (MMFR)
0xFC03_0044 MII Speed Control Register (MSCR)
0xFC03_0064 MIB Control/Status Register (MIBC)
0xFC03_0084 Receive Control Register (RCR)
0xFC03_00C4 Transmit Control Register (TCR)
19-6
Table 19-1. FEC Signal Descriptions (continued)
Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble
of a preamble and is negated before the first FEC_TXCLK following the final nibble of the frame.
one or more illegal symbols. FEC_TXER has no effect at 10 Mbps or when FEC_TXEN is
negated.
Table 19-2. Module Memory Map
Address
Table 19-3. FEC Register Memory Map
Register
MCF5329 Reference Manual, Rev 3
Description
Function
Control/Status Registers
MIB Block Counters
Width
Access Reset Value
(bits)
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0xF000_0000
32 R/W Undefined
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x05EE_0001
32 R/W 0x0000_0000
Section/Page
19.4.2/19-9
19.4.3/19-11
19.4.4/19-11
19.4.5/19-12
19.4.6/19-13
19.4.7/19-13
19.4.8/19-15
19.4.9/19-16
19.4.10/19-16
19.4.11/19-17
Freescale Semiconductor