Transfer Size - Freescale Semiconductor MCF5329 Reference Manual

SDRAM Controller (SDRAMC)
All SD_CS blocks are refreshed at the same time. The refresh closes all banks of every SDRAM block.
18.6.2

Transfer Size

In the SDRAMC, the internal data bus is 32 bits wide, while the SDRAM external interface bus is
32 or 16 bits wide. Therefore, each internal data beat requires one or two memory data beats. The SDRAM
controller manages the size translation (packing/unpacking) between internal and external DRAM buses.
The burst size is the processor standard 16 bytes: Four beats of 4 bytes on the internal bus, four beats of 4
bytes (32-bit mode), or eight beats of 2 bytes (16-bit mode) on the memory bus. The SDRAM controller
follows the critical beat first, sequential transfer format required.
The burst size and transfer order must be programmed in the SDRAM mode registers during initialization;
the burst size also must be programmed in the memory controller (SDCFG2 register).
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor 18-29