Pll Modulation Divider Register (Pmdr) - Freescale Semiconductor MCF5329 Reference Manual

Field
7 Dithering enable bit.
DITHEN 0 Dithering disabled.
1 Dithering enabled.
6–3 Reserved, should be cleared.
2–0 Dither Deviation. The dither deviation settings are target percentages based on simulation. The actual percentages
DITHDEV observed are slightly larger than these targets. See
information.
Deviation = -0.75% - (DITHDEV × 0.75%)
Note: This field should only be written when dithering mode is disabled (PCR[DITHEN] = 0). Else, unpredictable PLL
operation results.
7.2.3

PLL Modulation Divider Register (PMDR)

Address: 0xFC0C_0008 (PMDR)
7
R
W
Reset: 0
Freescale Semiconductor
Table 7-4. PCR Field Descriptions
DITHDEV
000
001
010
011
100
101
110
111
6 5
0 0
Figure 7-5. PLL Modulation Divider Register (PMDR)
MCF5329 Reference Manual, Rev 3
Description
Section 7.3.2, "Dithering Waveform Definition"
Deviation
- 0.75%
- 1.00%
- 1.25%
- 1.50%
- 1.75%
- 2.00%
- 2.25%
- 2.50%
4 3 2
MODDIV
0 0 0
Clock Module
for more
Access: User read/write
1 0
0 0
7-7