Freescale Semiconductor MCF5329 Reference Manual page 669

Internal Bus
Clock (f )
sys/3
26.3.1.1 Prescaled Clock (A or B)
The internal bus clock is the input clock to the PWM prescaler that can be disabled when the device is in
debug mode by setting the PWMCTL[PFRZ] bit. This is useful for reducing power consumption and for
emulation to freeze the PWM. The input clock is also disabled when all PWM channels are disabled
(PWMEn=0).
Clock A and B are scaled values of the input clock. The value is software selectable for clock A and B and
has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is
determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits.
Freescale Semiconductor
PWMSCLA
PWMPRCLK
[PCKA]
PWMSCLB
PWMPRCLK
[PCKB]
Figure 26-14. PWM Clock Select Block Diagram
MCF5329 Reference Manual, Rev 3
Pulse-Width Modulation (PWM) Module
1
0
1
0
PCLR1
Clock SA
1
÷2
0
1
0
Clock A Clock
PCLR5
PCLR2
Clock SB
1
÷2
0
1
0
Clock B
1
0
1
0
PCLR7
PCLR0
Clock to
PWM0
Clock to
PWM1
PCLR4
Clock to
PWM4
Clock to
PWM5
Clock to
PWM2
Clock to
PWM3
PCLR3
PCLR6
Clock to
PWM6
Clock to
PWM7
26-13