Freescale Semiconductor MCF5329 Reference Manual page 402

Fast Ethernet Controller (FEC)
Software may choose to mask off these interrupts because these errors are visible to network management
via the MIB counters.
Address: 0xFC03_0004
31 30 29
R HB
BABR BABT GRA
ERR
W w1c w1c w1c
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Field
31 Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window
HBERR following a transmission.
30 Babbling receive error. Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
BABR
29 Babbling transmit error. Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition
BABT is caused by a frame that is too long is placed into the transmit data buffer(s). Truncation does not occur.
28 Graceful stop complete. Indicates the graceful stop is complete. During graceful stop the transmitter is placed into a
GRA pause state after completion of the frame currently being transmitted. This bit is set by one of three conditions:
1) A graceful stop initiated by the setting of the TCR[GTS] bit is now complete.
2) A graceful stop initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.
3) A graceful stop initiated by the reception of a valid full duplex flow control pause frame is now complete. Refer
to Section 19.5.11, "Full Duplex Flow Control."
27 Transmit frame interrupt. Indicates a frame has been transmitted and the last corresponding buffer descriptor has
TXF been updated.
26 Transmit buffer interrupt. Indicates a transmit buffer descriptor has been updated.
TXB
25 Receive frame interrupt. Indicates a frame has been received and the last corresponding buffer descriptor has been
RXF updated.
24 Receive buffer interrupt. Indicates a receive buffer descriptor not the last in the frame has been updated.
RXB
23 MII interrupt. Indicates the MII has completed the data transfer requested.
MII
22 Ethernet bus error. Indicates a system bus error occurred when a DMA transaction is underway. When the EBERR
EBERR bit is set, ECR[ETHER_EN] is cleared, halting frame processing by the FEC. When this occurs, software needs to
ensure that the FIFO controller and DMA also soft reset.
21 Late collision. Indicates a collision occurred beyond the collision window (slot time) in half duplex mode. The frame
LC truncates with a bad CRC and the remainder of the frame is discarded.
19-10
28 27 26 25
TXF TXB RXF
w1c w1c w1c w1c
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
Figure 19-2. Ethernet Interrupt Event Register (EIR)
Table 19-5. EIR Field Descriptions
MCF5329 Reference Manual, Rev 3
24 23 22 21
EB
RXB MII LC
ERR
w1c w1c w1c w1c
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
Description
Access: User read/write
20 19 18 17
RL UN 0 0
w1c w1c
0 0 0 0
4 3 2 1
0 0 0 0
0 0 0 0
Freescale Semiconductor
16
0
0
0
0
0