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Liquid Crystal Display Controller (LCDC)
LCD_FLM
LCD_LP
LCD_LSCLK
LCD_D[17:0]
When it is in CSTN mode or monochrome mode with bus width = 1, T = 1 LCD_LSCLK period.
When it is in monochrome mode with bus width = 2, 4 and 8, T = 1, 2 and 4 LCD_LSCLK period respectively.
Figure 22-38. Horizontal Sync Pulse Timing in Passive Mode
LCD_FLM
LCD_LP
LCD_LSCLK
22.4.10 8 bpp Mode Color STN Panel
22.4.10.1 Active Matrix Panel Interface Signals
Figure 22-40
shows the LCD interface timing for an active matrix color TFT panel. In this figure, signals
are shown with negative polarity (FLMPOL=1, LPPOL=1, CLKPOL=0, OEPOL=1). In TFT mode, the
LCD_LSCLK is automatically inverted. The panel interface timing for active matrix panels is sometimes
referred to as a digital CRT and is controlled by the shift clock (LCD_LSCLK), horizontal sync pulse
(LCD_HSYNC, the LCD_LP pin in passive mode), vertical sync pulse (LCD_VSYNC, the LCD_FLM
pin in passive mode), output enable (LCD_OE, the LCD_ACD pin in passive mode), and line data
(LCD_D) signals. The sequence of events for active matrix interface timing is:
1. LCD_LSCLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, LCD_LSCLK runs continuously.
2. LCD_HSYNC causes the panel to start a new line.
22-40
Hwait2+2
(last line)
T
Hwidth+1
PASS_FRAME_WAIT
End of last line
Figure 22-39. Vertical Sync Pulse Timing in Passive Mode
MCF5329 Reference Manual, Rev 3
Hwait1+1
XMAX
Ts
YMAX
(lines)
Start of frame
Hwait2+2
(first line)
Hwidth+1
Freescale Semiconductor
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