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Table 33-7. MDISR & MDIMR Field Descriptions (continued)
Field
1
Reserved, should be cleared.
0
Input FIFO Overflow. Read only. The Input FIFO has been written to while full.
IFO
0 No overflow occurred
1 Input FIFO overflow error
33.2.6
MDHA Data Size Register (MDDSR)
The MDDSR stores the size of the last block of data to be processed. This value is in bytes. The first two
bits are used to identify the ending byte location in the last word. This is used to add the data padding when
auto padding is selected in the MDMR. Load this register with the amount of data to be processed in the
FIFO. This register is cleared when the MDHA is reset, re-initialized and at the end of processing the
complete message.
Address: 0xEC08_001C (MDDSR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
33.2.7
MDHA Input FIFO (MDIN)
The MDIN provides temporary storage for data to be used during hashing. The FIFO is a write only
register and attempting to read from this register always returns 0. If the FIFO is written to when the FIFO
Level is full, an interrupt request is generated and the MDISR[IFO] bit is set. The MDSR[IFL], described
in
Section 33.2.4, "MDHA Status Register (MDSR),"
longwords are currently resident in the FIFO.
Address: 0xEC08_0020 (MDIN)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
33.2.8
MDHA Message Digest Registers 0 (MDx0)
The MDHA message digest registers 0 consist of five 32-bit registers (MDA0, MDB0, MDC0, MDD0,
and MDE0). These registers store the five (SHA-1) or four (MD5) 32-bit longwords that are the final
answer (digest/context) of the hashing process. Message digest data may only be read if the
MDSR[DONE] bit is set. Any reads prior to this result is an early read error (MDISR[ERE]). The message
Freescale Semiconductor
Description
Figure 33-8. MDHA Data Size Register (MDDSR)
Input FIFO
Figure 33-9. MDHA Input FIFO (MDIN)
MCF5329 Reference Manual, Rev 3
Message Digest Hardware Accelerator (MDHA)
8
MDHA Data Size
can be polled to monitor how many 32-bit
8
Access: User read/write
7
6
5
4
3
2
1
0
Access: User write-only
7
6
5
4
3
2
1
0
33-11
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