Saved Level Mask Register (Slmask) - Freescale Semiconductor MCF5329 Reference Manual

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329
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Interrupt Controller Modules
Only one copy of this register exists among the 2 interrupt controller
modules. All reads and writes to this register must be made to the INTC0
memory space.
Address: 0xFC04_801E (CLMASK)
7
R
0
W
Reset:
0
Field
7–4
Reserved, must be cleared.
3–0
Current level mask. Defines the level mask, where only interrupt levels greater than the current value are processed
CLMASK
by the controller
0000 Level 1 – 7 requests are processed.
0001 Level 2 – 7 requests are processed.
0010 Level 3 – 7 requests are processed.
0011 Level 4 – 7 requests are processed.
0100 Level 5 – 7 requests are processed.
0101 Level 6 – 7 requests are processed.
0110 Level 7 requests are processed.
0111 All requests are masked.
1000 – 1110 Reserved.
1111 Level 1 – 7 requests are processed.
14.2.8

Saved Level Mask Register (SLMASK)

The SLMASK register is provided so the interrupt controller can optionally automatically manage
masking of interrupt requests based on the programmed priority level. If enabled by ICONFIG[EMASK]
bit being set, an interrupt acknowledge read cycle returns a vector number identifying the physical request
source, and the CLMASK register is loaded with the level number associated with the request. After the
CLMASK register is updated, then all interrupt requests with level numbers equal to or less than this value
are masked by the controller and are not allowed to cause the assertion of the interrupt signal to the
processor core. As the CLMASK register is updated during the IACK cycle read, the former value is saved
in the SLMASK register.
Typically, after a level-n interrupt request is managed, the service routine restores the saved level mask
value into the current level mask register to re-enable the lower priority requests.
Only one copy of this register exists among the two interrupt controller
modules. All reads and writes to this register must be made to the INTC0
memory space.
14-10
NOTE
6
5
0
0
0
0
Figure 14-10. Current Level Mask Register (CLMASK)
Table 14-12. CLMASK Field Descriptions
NOTE
MCF5329 Reference Manual, Rev 3
4
3
2
0
0
1
1
Description
Access: User read/write
1
0
CLMASK
1
1
Freescale Semiconductor

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