Freescale Semiconductor MCF5329 Reference Manual page 729

Field
1 FIFO full.
FFULL 0 The FIFO is not full but may hold up to two unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost.
0 Receiver ready.
RXRDY 0 The CPU has read the receive buffer and no characters remain in the FIFO after this read.
1 One or more characters were received and are waiting in the receive buffer FIFO.
31.3.4 UART Clock Select Registers (UCSRn)
The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus
clock as the clocking source for the transmitter and receiver. See
Clock Source." The transmitter and receiver can use different clock sources. To use the internal bus clock
for both, set UCSRn to 0xDD.
Address: 0xFC06_0004 (UCSR0)
0xFC06_4004 (UCSR1)
0xFC06_8004 (UCSR2)
7
R
W
Reset:
Note: The RCS and TCS reset values are set so the receiver and transmiter use the prescaled internal bus
clock as their clock source.
Field
7–4 Receiver clock select. Selects the clock source for the receiver.
RCS 1101 Prescaled internal bus clock (f
1110 DTnIN divided by 16
1111 DTnIN
3–0 Transmitter clock select. Selects the clock source for the transmitter.
TCS 1101 Prescaled internal bus clock (f
1110 DTnIN divided by 16
1111 DTnIN
31.3.5 UART Command Registers (UCRn)
The UCRs supply commands to the UART. Only multiple commands that do not conflict can be specified
in a single write to a UCRn. For example,
specified in one command.
Freescale Semiconductor
Table 31-5. USRn Field Descriptions (continued)
6 5 4
RCS
See Note
Figure 31-6. UART Clock Select Registers (UCSRn)
Table 31-6. UCSRn Field Descriptions
)
sys/3
)
sys/3
RESET TRANSMITTER
MCF5329 Reference Manual, Rev 3
Description
Section 31.4.1, "Transmitter/Receiver
3 2
See Note
Description
and
ENABLE TRANSMITTER
UART Modules
Access: User write-only
1 0
TCS
cannot be
31-9