Features - Freescale Semiconductor MCF5329 Reference Manual

12.2

Features

The crossbar switch includes these distinctive features:
• Symmetric crossbar bus switch implementation
— Allows concurrent accesses from different masters to different slaves
— Slave arbitration attributes configured on a slave by slave basis
• 32 bits wide and supports byte, word (2 byte), longword (4 byte), and 16 byte burst transfers
• Operates at a 1-to-1 clock frequency with the bus masters
12.3 Modes of Operation
The crossbar switch supports two arbitration modes (fixed or round-robin), which may be set on a slave
by slave basis. Slaves configured for fixed arbitration mode have a unique arbitration level assigned to
each bus master.
In fixed priority mode, the highest priority active master accessing a particular slave is granted the master
bus path to that slave. A higher priority master blocks access to a given slave from a lower priority master
if the higher priority master continuously requests that slave. See
Operation."
In round-robin arbitration, active masters accessing a particular slave are initially granted the slave based
on their master port number. Master priority is then modified in a wrap-around manner to give all masters
fair access to the slave. See
12.4 Memory Map / Register Definition
Two registers reside in each slave port of the crossbar switch. Read- and write-transfers require two bus
clock cycles. The registers can only be read from and written to in supervisor mode. Additionally, these
registers can only be read from or written to by 32-bit accesses.
A bus error response is returned if an unimplemented location is accessed within the crossbar switch. See
Section 11.2.7, "SCM Interrupt Status Register (SCMISR)."
The slave registers also feature a bit that, when set, prevents the registers from being written. The registers
remain readable, but future write attempts have no effect on the registers and are terminated with a bus
error response to the master initiating the write. The core, for example, takes a bus error interrupt.
Table 12-2 shows the memory map for the crossbar switch program-visible registers.
Address
0xFC00_4100 Priority Register Slave 1 (XBS_PRS1)
0xFC00_4110 Control Register Slave 1 (XBS_CRS1)
0xFC00_4400 Priority Register Slave 4 (XBS_PRS4)
0xFC00_4410 Control Register Slave 4 (XBS_CRS4)
Freescale Semiconductor
Section 12.5.1.2, "Round-Robin Priority Operation."
Table 12-2. XBS Memory Map
Register
MCF5329 Reference Manual, Rev 3
Crossbar Switch (XBS)
Section 12.5.1.1, "Fixed-Priority
Width
Access Reset Value Section/Page
(bits)
32 R/W 0x6543_0210
32 R/W 0x0000_0000
32 R/W 0x6543_0210
32 R/W 0x0000_0000
12.4.1/12-4
12.4.2/12-5
12.4.1/12-4
12.4.2/12-5
12-3