Freescale Semiconductor MCF5329 Reference Manual page 852

Debug Module
Command Sequence:
WCREG MS ADDR
??? 'NOT READY'
Operand Data: This instruction requires two longword operands. The first selects the register to
the operand data writes to; the second contains the data.
Result Data: Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern of
0x0001.
36.4.1.5.14 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the RDMREG command is CSR.
Command/Result Formats:
15 14
Command
Result
Table 36-22 shows the definition of DRc encoding.
DRc[4:0]
36-36
MS ADDR
'NOT READY'
Figure 36-38.
WCREG
13 12 11 10
0x2 0xD
Figure 36-39.
RDMREG
Table 36-22. Definition of DRc Encoding—Read
Debug Register Definition
0x00 Configuration/Status
MCF5329 Reference Manual, Rev 3
MS DATA
'NOT READY'
WRITE
LS DATA
CONTROL
'NOT READY'
REGISTER
Command Sequence
)
RDMREG
9 8 7 6 5
100
D[31:16]
D[15:0]
Command/Result Formats
Mnemonic
XXX
'NOT READY'
NEXT CMD
'CMD COMPLETE'
XXX
BERR
NEXT CMD
'NOT READY'
4 3 2 1 0
DRc
CSR
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