Freescale Semiconductor MCF5329 Reference Manual page 380

SDRAM Controller (SDRAMC)
Address: 0xFC0B_8008 (SDCFG1)
31 30 29
R
SRD2RWP
W
Reset 0 0 0
15 14 13
R 0
PRE2ACT
W
Reset 0 0 0
Field
31–28 Single read to read/write/precharge delay. Limiting case is read to write.
SRD2RWP SDR: SRD2RWP = CL
DDR: SRD2RWP = CL + 1
t is the time the data bus uses to return to hi-impedance after a read and is found in the SDRAM device
HZ
specifications.
Note: Count value is in SD_CLK periods for SDR and DDR mode.
27 Reserved, must be cleared.
26–24 Single write to read/write/precharge delay. Limiting case is write to precharge.
SWT2RWP SDR: SWT2RWP = t
DDR: SWT2RWP = t
Note: Count value is in SD_CLK periods for SDR and DDR mode.
23–20 Read CAS Latency. Read command to read data available delay counter.
RD_LAT For DDR:
If CL = 2, write 0x6
If CL = 2.5, write 0x7
For SDR:
If CL = 2, write 0x2
If CL = 3, write 0x3
Note: The recommended values are just a starting point and may need to be adjusted depending on the trace
length for the data and DQS lines.
CL = 2.5 is not supported for SDR.
SDR: Count value is in SD_CLK periods.
DDR: Count value is in SD_CLK2 periods.
19 Reserved, must be cleared.
18–16 Active to read/write delay. Active command to any following read- or write-delay counter.
ACT2RW
Suggested value = (t
Example:
If t = 20ns and f
RCD
Suggested value = (20ns × 99 MHz) - 1= 0.98; round to 1.
Note: Count value is in SD_CLK periods for SDR and DDR modes.
18-18
28 27 26 25
0
SWT2RWP
0 0 0 0
12 11 10 9
REF2ACT
0 0 0 0
Figure 18-7. SDRAM Configuration Register 1 (SDCFG1)
Table 18-9. SDCFG1 Field Descriptions
+ t
+ 2
HZ
WR
+ 1
WR
× f
) - 1 (Round up to nearest integer)
RCD SD_CLK
= 99 MHz
SD_CLK
MCF5329 Reference Manual, Rev 3
24 23 22 21
RD_LAT
0 0 0 0
8 7 6 5
0
WT_LAT
0 0 0 0
Description
Access: User read/write
20 19 18 17
0
ACT2RW
0 0 0 0
4 3 2 1
0 0 0
0 0 0 0
Freescale Semiconductor
16
0
0
0
0