Sir Mode; Mir Mode; Data Format - Freescale Semiconductor MCF5480 Reference Manual

Leaving low power mode can be done via either a warm or cold reset
a warm reset by writing a 1 to the AWR bit of SICR register for a minimum of 1 us. The AWR bit forces
a 1 on PSCnRTS, which is used as the frame sync output in AC97 mode. The pulse width of warm or cold
reset should be dependent on AC97 codec chip.
RESET
PSCBCLK
26.4.6

SIR Mode

The data format in SIR mode is similar to that of UART mode. Each data consists of a start bit, 8 bit data,
and a stop bit. Each bit of data is encoded so that a 0 is encoded as 3/16 of the bit time pulse (or 1.6 υs
pulse), and a 1 is encoded as no pulse. Similarly, the received serial pulse is decoded as a 0, and an absence
of a pulse is decoded as a 1.
UART Data Format
SIR Data Format
26.4.7

MIR Mode

26.4.7.1 Data Format

The encoded pulse width of data in MIR mode is 1/4 of the bit duration and the transfer is synchronous.
Binary Data 0
The packet format is similar to HDLC packet format
STA
01111110
Freescale Semiconductor
Cold reset
Figure 26-34. AC97 Cold and Warm Reset
Figure 26-35 is an example of data stream of UART and SIR.
START Bit
0 1
3/16 of the bit width or 1.6 µs
Figure 26-35. Data Format in SIR Mode
Flag
1 1 1 1 1 1 0
1/4 of the bit width
Figure 26-36. Data Format in MIR Mode
STA
01111110
Figure 26-37. MIR Packet Format
MCF548x Reference Manual, Rev. 3
(Figure
PSCFSYNC
PSCBCLK
Warm reset
Data Bits (8-bit)
0 1 0 1 1
Character FE
0 1 1 1 1 1
DATA FCS
16-bit CRC
Functional Description
26-34). The CPU performs
STOP Bit
0 0 1
0 1 1 0 1 0 1
STO
01111110
26-41