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Security Engine (SEC)
In addition to the basic registers, an EU also includes specific registers and data structures to
support the individual computational requirements. The register and structure types can include:
Input FIFOs and/or output FIFOs
End_of_Message Registers
Key registers and key memory
Context registers and context memory and context memory pointers
Special purpose registers for ABSize, EU-GO, IV, ICV, and data registers
Refer to the individual EU functional descriptions for a list the registers for that EU and to
Section 26.5, Programming Model, on page 26-66 for a detailed description of each register and
associated register fields.
26.4.1 Public Key Execution Unit (PKEU)
The public key execution unit (PKEU) is typically operated through channel-controlled access,
which means that most reads and writes of PKEU registers are directed by the SEC channels.
Driver software performs core processor-controlled register accesses only on a few registers for
initial configuration and error handling.
The following subsections include general descriptions of the PKEU registers and structures.
Section 26.5, Programming Model, on page 26-66 provides a detailed description of each
register and associated register fields.
26.4.1.1 PKEU Mode Register
This register pacifies the internal PKEU routine to execute. The Mode Register is cleared when
the PKEU is reset or reinitialized. Setting a reserved mode bit generates a data error. If the Mode
Register is modified during processing, a context error is generated.
26.4.1.2 PKEU Key Size Register
The register reflects the number of significant bytes to use from PKEU Parameter Memory E in
performing modular exponentiation or elliptic curve point multiplication. The range of values for
this register when performing either modular exponentiation or elliptic curve point multiplication
is from 1 to 256. Specifying a key size outside this range causes a key size error (KSE) in the
PKEU Interrupt Status Register.
26.4.1.3 PKEU AB Size Register
This register represents the operand size for the specific operands whenever required. The AB
size is in bits even though internally, the PKEU imposes 32-bit alignment. Any data beyond the
number specified by the AB Size Register, either in A and B-ram (operands), is ignored. Because
no error checking is performed, having an operand size greater than the prime modulus or the
field size may result is a wrong result. It is assumed that operands are modulo reduced before
26-24
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
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