ST STM32G0 1 Series Reference Manual page 1188

Serial peripheral interface / integrated interchip sound (SPI/I2S)
Bits 11:8 DS[3:0]: Data size
Note: These bits are not used in I
Bit 7 TXEIE: Tx buffer empty interrupt enable
Bit 6 RXNEIE: RX buffer not empty interrupt enable
Bit 5 ERRIE: Error interrupt enable
Bit 4 FRF: Frame format
Note: This bit must be written only when the SPI is disabled (SPE=0).
Bit 3 NSSP
It has no meaning if CPHA = '1', or FRF = '1'.
Note: 1. This bit must be written only when the SPI is disabled (SPE=0).
1188/1390
These bits configure the data length for SPI transfers.
0000: Not used
0001: Not used
0010: Not used
0011: 4-bit
0100: 5-bit
0101: 6-bit
0110: 7-bit
0111: 8-bit
1000: 9-bit
1001: 10-bit
1010: 11-bit
1011: 12-bit
1100: 13-bit
1101: 14-bit
1110: 15-bit
1111: 16-bit
If software attempts to write one of the "Not used" values, they are forced to the value "0111"
(8-bit)
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is
set.
This bit controls the generation of an interrupt when an error condition occurs (CRCERR,
OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I
0: Error interrupt is masked
1: Error interrupt is enabled
0: SPI Motorola mode
1 SPI TI mode
This bit is not used in I
NSS pulse management
:
This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two
consecutive data when doing continuous transfers. In the case of a single data transfer, it
forces the NSS pin high level after the transfer.
0: No NSS pulse
1: NSS pulse generated
2. This bit is not used in I
2
S mode.
2
S mode.
2
S mode and SPI TI mode.
RM0444 Rev 5
RM0444
2
S mode).