Structure Of The Can Core's Can Protocol Controller - Texas Instruments TMS320F28004x Technical Reference Manual

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Figure 24-14. Structure of the CAN Core's CAN Protocol Controller
System clock
Receive_Data
Transmit_Data
In this bit timing register, the components TSEG1, TSEG2, SJW and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1...n],
values in the range of [0...n-1] are programmed. That way, for example, SJW (functional range of [1...4])
is represented by only two bits.
Therefore the length of the Bit time is (programmed values) [TSEG1 + TSEG2 + 3] t
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] t
The data in the Bit Timing Register is the configuration input of the CAN protocol controller. The baud rate
prescaler (configured by BRPE/BRP) defines the length of the time quantum (the basic time unit of the bit
time); the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in
the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and occasional
synchronizations are controlled by the Bit timing state machine, which is evaluated once each time
quantum. The rest of the CAN protocol controller, the Bit Stream Processor (BSP) state machine, is
evaluated once each bit time, at the Sample Point.
The Shift register serializes the messages to be sent and parallelizes received messages. Its loading and
shifting is controlled by the BSP.
The BSP translates messages into frames and vice versa. It generates and discards the enclosing fixed
format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the error
management, and decides which type of synchronization is to be used. It is evaluated at the sample point
and processes the sampled bus input bit. The time after the sample point that is needed to calculate the
next bit to be sent (for example, data bit, CRC bit, stuff bit, error flag, or idle) is called the Information
Processing Time (IPT), which is 0 t
Generally, the IPT is CAN controller specific, but may not be longer than 2 t
limit of the programmed length of Phase_Seg2. In case of a synchronization, Phase_Seg2 may be
shortened to a value less than IPT, which does not affect bus timing.
24.13.2.1 Calculation of the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time. The resulting
Bit time (1 / Bit rate) must be an integer multiple of the CAN clock period.
SPRUI33 – November 4 2015 – Revised January 2017
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Configuration (BRPE/BRP)
Scaled_Clock (tq)
Baudrate_
prescaler
Bit
timing
logic
Next_Data_Bit
Configuration (TSEG1, TSEG2, SJW)
for the CAN.
q
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Sample_Point
Sampled_Bit
Sync_Mode
Bit_to_send
Bus-Off
Control
Shift-Register
.
q
CAN Bit Timing
Control
Status
Received_Data_Bit
Send_Message
Received_Message
or (functional values)
q
. The IPT length is the lower
q
Controller Area Network (CAN)
2013