Bits 12 To 14: Processor Interrupt Priority Level (Ipl); Bit 15: Reserved - Renesas R8C/Tiny Series Software Manual

Chapter 1 Overview

1.4.10 Bits 12 to 14: Processor Interrupt Priority Level (IPL)

The processor interrupt priority level (IPL) consists of three bits, enabling specification of eight proces-
sor interrupt priority levels from level 0 to level 7. If a requested interrupt's priority level is higher than the
processor interrupt priority level (IPL), the interrupt is enabled.

1.4.11 Bit 15: Reserved

b15
IPL
Figure 1.4.1 Configuration of Flag Register (FLG)
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
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b0
O B S Z D C
1.4 Flag Register (FLG)
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area