Sci3 Initialization; Figure 14.5 Sample Sci3 Initialization Flowchart - Renesas H8/36912 Series User Manual

16-bit single-chip microcomputer
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14.4.2

SCI3 Initialization

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0,
then initialize SCI3 as described below. When the operating mode, or transfer format, is changed
for example, the TE and RE bits must be cleared to 0 before making the change using the
following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the
contents of RDR. When the external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
SCR3 to 1, and set RIE, TIE, TEIE,
and MPIE bits. For transmit (TE=1),
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Start initialization
Clear TE and RE bits in SCR3 to 0
Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
Set value in BRR
Wait
1-bit interval elapsed?
Yes
Set TE and RE bits in
also set the TxD bit in PMR1.
<Initialization completion>

Figure 14.5 Sample SCI3 Initialization Flowchart

[1]
Set the clock selection in SCR3.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
[1]
settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
[2]
immediately after CKE1, CKE0, and RE
are set to 1.
[2]
Set the data transfer format in SMR.
[3]
[3]
Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
No
[4]
Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1. RE
settings enable the RXD pin to be used.
For transmission, set the TXD bit in
PMR1 to 1 to enable the TXD output pin
[4]
to be used. Also set the RIE, TIE, TEIE,
and MPIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
transmission and idled at reception to
wait for the start bit.
For transmission, set the TE bit to 1 and
then output 1 for one frame to enable.
Rev. 1.00, 11/03, page 203 of 376

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