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1.2 Block Diagram
www.DataSheet4U.com
Figure 1-1 shows an internal block diagram.
MD
2
MD
1
MD
0
EXTAL
XTAL
ø
STBY
RES
V
*
/RESO
PP
NMI
P6 /LWR
6
P6 /HWR
5
P6 /RD
4
P6 /AS
3
P6 /BACK
2
P6 /BREQ
1
P6 /WAIT
0
P8 /CS
4
0
P8 /CS /IRQ
3
1
3
P8 /CS /IRQ
2
2
2
P8 /CS /IRQ
1
3
1
P8 /RFSH/IRQ
0
0
Note: * V
function is provided only for the flash memory version.
PP
Port 3
H8/300H CPU
Interrupt controller
ROM
(masked ROM,
PROM, or flash
memory)
RAM
16-bit integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
Port B
Port A
Figure 1-1 Block Diagram
5
Port 4
Address bus
Data bus (upper)
Data bus (lower)
DMA controller
(DMAC)
Refresh
controller
Watchdog timer
(WDT)
Serial communication
interface
×
(SCI)
2 channels
A/D converter
D/A converter
Port 7
P5 /A
3
19
P5 /A
2
18
P5 /A
1
17
P5 /A
0
16
P2 /A
7
15
P2 /A
6
14
P2 /A
5
13
P2 /A
4
12
P2 /A
3
11
P2 /A
2
10
P2 /A
1
9
P2 /A
0
8
P1 /A
7
7
P1 /A
6
6
P1 /A
5
5
P1 /A
4
4
P1 /A
3
3
P1 /A
2
2
P1 /A
1
1
P1 /A
0
0
P9 /SCK /IRQ
5
1
5
P9 /SCK /IRQ
4
0
4
P9 /RxD
3
1
P9 /RxD
2
0
P9 /TxD
1
1
P9 /TxD
0
0
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