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1.2 Internal Block Diagram
Figure 1-1 shows a block diagram of the H8/3867 Series and H8/3827 Series.
P1
/TMOW
0
P1
/TMOFL
1
P1
/TMOFH
2
P1
/TMIG
3
P1
/IRQ
/ADTRG
4
4
P1
/IRQ
/TMIC
5
1
P1
/IRQ
6
2
P1
/IRQ
/TMIF
7
3
P3
/PWM
0
P3
/UD
1
P3
/RESO
2
P3
/SCK
3
31
P3
/RXD
4
31
P3
/TXD
5
31
P3
/AEVH
6
P3
/AEVL
7
P4
/SCK
0
32
P4
/RXD
1
32
P4
/TXD
2
32
P4
/IRQ
3
0
P5
/WKP
/SEG
0
0
1
P5
/WKP
/SEG
1
1
2
P5
/WKP
/SEG
2
2
3
P5
/WKP
/SEG
3
3
4
P5
/WKP
/SEG
4
4
5
P5
/WKP
/SEG
5
5
6
P5
/WKP
/SEG
6
6
7
P5
/WKP
/SEG
7
7
8
ROM
(60k/48k/40k/32k
24k/16k)
Timer - A
Timer - C
Timer - F
Timer - G
Asynchronous
counter
A/D
(10bit)
Figure 1-1 Block Diagram
H8/300L
CPU
RAM
(2k/1k)
Serial
communication
interface 3-1
Serial
communication
interface 3-2
14-bit
PWM
WDT
LCD
Controller
Port B
5
V
0
V
1
V
2
V
3
PA
/COM
3
4
PA
/COM
2
3
PA
/COM
1
2
PA
/COM
0
1
P8
/SEG
/CL
7
32
1
P8
/SEG
/CL
6
31
2
P8
/SEG
/DO
5
30
P8
/SEG
/M
4
29
P8
/SEG
3
28
P8
/SEG
2
27
P8
/SEG
1
26
P8
/SEG
0
25
P7
/SEG
7
24
P7
/SEG
6
23
P7
/SEG
5
22
P7
/SEG
4
21
P7
/SEG
3
20
P7
/SEG
2
19
P7
/SEG
1
18
P7
/SEG
0
17
P6
/SEG
7
16
P6
/SEG
6
15
P6
/SEG
5
14
P6
/SEG
4
13
P6
/SEG
3
12
P6
/SEG
2
11
P6
/SEG
1
10
P6
/SEG
0
9
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