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1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/532 chip.
EXTAL
XTAL
RES
STBY
MD
0
MD
1
MD
2
NMI
V
cc
V
cc
V
ss
V
ss
V
ss
*
V
ss
V
ss
V
ss
AV
cc
AV
ss
* CP-84 and CG-84 only
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Port 1
Clock
Gener-
ator
Wait-
RAM
State
1 kByte
Controller
Interrupt
Controller
Data
Transfer
Controller
Serial
Communication
Interface
PWM Timer
(x 3 channel)
10 Bits
A/D Converter
Port 9
Figure 1-1 Block Diagram
Port 2
Port 3
PROM/Mask
ROM 32 kByte
CPU
8 Bits Timer
16 Bits Free
Running Timer
(x 3 channel)
Watchdog
Timer
Port 8
Port 7
4
P4 /A
7
7
P4 /A
6
6
P4 /A
5
5
P4 /A
4
4
P4 /A
3
3
P4 /A
2
2
P4 /A
1
1
P4 /A
0
0
P5 /A
7
15
P5 /A
6
14
P5 /A
5
13
P5 /A
4
12
P5 /A
3
11
P5 /A
2
10
P5 /A
1
9
P5 /A
0
8
P6 /A
3
19
P6 /A
2
18
P6 /A
1
17
P6 /A
0
16
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