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1.2
Block Diagram
MMU
TLB
CCN
CACHE
ASERAM
UDI
INTC
CPG/WDT
Legend:
ADC:
A/D converter
ASERAM:
ASE memory
AUD:
Advanced user debugger
BSC:
Bus state controller
CACHE:
Cache memory
CCN:
Cache memory controller
CMT:
Compare match timer
CPG/WDT:
Clock pulse generator/watchdog timer
CPU:
Central processing unit
DAC:
D/A converter
DMAC:
Direct memory access controller
H-UDI:
Hitachi user-debugging interface
6
BRIDGE
External bus
interface
INTC:
IrDA:
MMU:
RTC:
SCI:
SCIF:
TLB:
TMU:
UBC:
Figure 1.1 Block Diagram
SH-3
CPU
UBC
AUD
SCI
TMU
RTC
BSC
IrDA
SCIF
DMAC
ADC
CMT
DAC
I/O port
Interrupt controller
Serial communicatiion interface (with IrDA)
Memory management unit
Realtime clock
Serial communication interface (with smart card interface)
Serial communication interface (with FIFO)
Address translation buffer
Timer unit
User break controller
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