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1.2 Block Diagram
Figure 1-1 shows an internal block diagram.
MD
1
MD
0
EXTAL
XTAL
ø
STBY
RES
RESO
NMI
P6
/WR
5
P6
/RD
4
P6
/AS
3
P6
/WAIT
0
P8
/IRQ
3
3
P8
/IRQ
2
2
P8
/IRQ
1
1
P8
/IRQ
0
0
Port B
Note: PROM version is available only in the H8/3032 Series.
Port 3
Address bus
Data bus (upper)
Data bus (lower)
H8/300H CPU
PROM*
Interrupt
(or masked
controller
ROM)
Watchdog
RAM
timer
(WDT)
Serial
16-bit
communication
integrated
interface
timer-pulse unit
(SCI) × 1 channel
(ITU)
Programmable
A/D converter
timing pattern
controller (TPC)
Port A
Figure 1-1 Block Diagram
5
P5
/A
3
15
P5
/A
2
16
P5
/A
1
17
P5
/A
0
18
P2
/A
7
15
P2
/A
6
14
P2
/A
5
13
P2
/A
4
12
P2
/A
3
11
P2
/A
2
10
P2
/A
1
9
P2
/A
0
8
P1
/A
7
7
P1
/A
6
6
P1
/A
5
5
P1
/A
4
4
P1
/A
3
3
P1
/A
2
2
P1
/A
1
1
P1
/A
0
0
P9
/SCK/IRQ
4
4
P9
/RxD
2
P9
/TxD
0
Port 7
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