Block Diagram - Hitachi F-ZTAT H8/3039 Series Hardware Manual

1.2 Block Diagram

Figure 1-1 shows an internal block diagram of the H8/3039 Series.
MD
2
MD
1
MD
0
EXTAL
XTAL
ø
STBY
RES
RESO/FWE*
NMI
P6 /WR
5
P6 /RD
4
P6 /AS
3
P6 /WAIT
0
P8 /IRQ
1 1
P8 /IRQ
0 0
ROM
(Flash memory,
masked ROM)
RAM
16-bit
integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
Port B
Note: * Masked ROM : RESO
Flash memory: FWE
Figure 1-1 Block Diagram
Port 3
Data bus (upper)
Data bus (lower)
H8/300H CPU
Interrupt
controller
Watchdog
timer
(WDT)
Serial
communication
interface
(SCI) × 2 channel
A/D converter
Port A
Address bus
P5 /A
3 19
P5 /A
2 18
P5 /A
1 17
P5 /A
0 16
P2 /A
7 15
P2 /A
6 14
P2 /A
5 13
P2 /A
4 12
P2 /A
3 11
P2 /A
2 10
P2 /A
1 9
P2 /A
0 8
P1 /A
7 7
P1 /A
6 6
P1 /A
5 5
P1 /A
4 4
P1 /A
3 3
P1 /A
2 2
P1 /A
1 1
P1 /A
0 0
P9 /SCK
5
P9 /SCK
4
P9 /RxD
3
P9 /RxD
2
P9 /TxD
1
P9 /TxD
0
Port 7
/IRQ
1 5
/IRQ
0 4
1
0
1
0
5