Conflict Between Tgr Write And Compare Match; Figure 10.47 Conflict Between Tgr Write And Compare Match - Hitachi H8S/2628 Hardware Manual

10.9.6

Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the previous
value is written.
Figure 10.47 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR

Figure 10.47 Conflict between TGR Write and Compare Match

Rev. 1.0, 09/02, page 234 of 568
TGR write cycle
T1 T2
TGR address
N N+1
N M
TGR write data
Inhibited