Notes On Use; Wtcnt Write And Increment Contention; Changing Cks2 To Cks0 Bit Values; Changing Watchdog Timer/Interval Timer Modes - Hitachi SH7095 Hardware User Manual

12.4

Notes on Use

12.4.1

WTCNT Write and Increment Contention

If a timer counter clock pulse is generated during the T3 state of a write cycle to the WTCNT, the
write takes priority and the timer counter is not incremented (figure 12.8).
Figure 12.8 Contention between WTCNT Write and Increment
12.4.2

Changing CKS2 to CKS0 Bit Values

If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may
increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
12.4.3

Changing Watchdog Timer/Interval Timer Modes

To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
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