Contention Between Tcor Write And Compare Match - Hitachi H8/3062 Hardware Manual

9.7.3

Contention between TCOR Write and Compare Match

If a compare match occurs in the T
compare match signal is inhibited. Figure 9.20 shows the timing in this case.
Address bus
Internal write signal
8TCNT
TCOR
Compare match signal
Figure 9.20 Contention between TCOR Write and Compare Match
state of a TCOR write cycle, writing takes priority and the
3
T
1
φ
N
N
TCOR write cycle
T
2
TCOR address
TCOR write data
T
3
N+1
M
Inhibited
311