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10.7.3
Contention between TCOR Write and Compare Match
If a compare match occurs in the T
compare match signal is inhibited. Figure 10.20 shows the timing in this case.
φ
Address bus
Internal write signal
8TCNT
TCOR
Compare match signal
Figure 10.20 Contention between TCOR Write and Compare Match
state of a TCOR write cycle, writing takes priority and the
3
TCOR write cycle
T
T
1
2
TCOR address
N
N
T
3
N+1
M
TCOR write data
Inhibited
375
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