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Contention between OCR Write and Compare-Match: If a compare-match occurs during the
T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and the
compare-match signal is inhibited.
Figure 10-14 shows this type of contention.
Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the FRC to increment. This depends on the time at
which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 10-5.
The pulse that increments the FRC is generated at the falling edge of the internal clock source. If
clock sources are changed when the old source is High and the new source is Low, as in case No.
3 in table 10-5, the changeover generates a falling edge that triggers the FRC increment pulse.
Switching between an internal and external clock source can also cause the FRC to increment.
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Write cycle: CPU write to lower byte of OCRA or OCRB
ø
Internal address bus
Internal write signal
FRC
OCRA or OCRB
Compare-match
A or B signal
Figure 10-14 Contention between OCR Write and Compare-Match
T
T
T
1
2
OCR address
N
N
Write data
203
3
N + 1
M
Inhibited
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