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11.8.3
Contention between TCOR Write and Compare Match
During the T
state of a TCOR write cycle, the TCOR write has priority and the compare match
2
signal is inhibited even if a compare match event occurs. In TMR, when ICR input capture and
compare match event occur at the same time, the ICR input capture has priority and the compare
match signal is inhibited. Figure 11.12 shows this operation.
ø
Address
Internal write signal
TCNT
TCOR
Compare match signal
Figure 11.12 Contention between TCOR Write and Compare Match
TCOR write cycle by CPU
T1
T2
TCOR address
N
N
N+1
M
TCOR write data
Disabled
Rev. 3.0, 10/02, page 343 of 686
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