Conflict Between Tgr Read And Input Capture; Figure 10.49 Conflict Between Tgr Read And Input Capture - Hitachi H8S/2628 Hardware Manual

10.9.8

Conflict between TGR Read and Input Capture

If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 10.49 shows the timing in this case.
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus

Figure 10.49 Conflict between TGR Read and Input Capture

Rev. 1.0, 09/02, page 236 of 568
TGR read cycle
T1 T2
TGR address
X M
M