Figure 10.49 Contention Between Tgr Read And Input Capture; Figure 10.50 Contention Between Tgr Write And Input Capture - Hitachi H8S/2215 Series Hardware Manual

φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus

Figure 10.49 Contention between TGR Read and Input Capture

Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed. Figure 10.50 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR

Figure 10.50 Contention between TGR Write and Input Capture

Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and
the write to the buffer register is not performed. Figure 10.51 shows the timing in this case.
TGR read cycle
T1 T2
TGR address
X M
M
TGR write cycle
T1 T2
TGR address
M
M
Rev. 3.0, 10/02, page 323 of 686