Input Capture Input Timing - Hitachi SH7095 Hardware User Manual

11.4.4

Input Capture Input Timing

The input of an input capture can be selected to be either the rising edge or falling edge, using the
IEDG bit of the TCR. Figure 11.8 shows the timing when the rising edge is selected (IEDG = 1).
Figure 11.8 Input Capture Signal Timing (Normal)
When the FICR is read (upper byte read) and the input capture signal is input, the input capture
signal is delayed one cycle of the clock that drives the timer. Figure 11.9 shows the timing.
Note: When FICR is read and input capture input is input
Figure 11.9 Input Capture Signal Timing
300 Hitachi