Irq Enable Register (Ier) - Hitachi H8/3006 Hardware Manual

5.2.4

IRQ Enable Register (IER)

IER is an 8-bit readable/writable register that enables or disables IRQ
Bit 7
—
Initial value 0
Read/Write R/W
Reserved bits
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0—IRQ to IRQ
5
IRQ to IRQ interrupts.
5 0
Bits 5 to 0
IRQ5E to IRQ0E Description
0 IRQ
1 IRQ
6 5
— IRQ5E
0 0
R/W R/W
Enable (IRQ5E to IRQ0E): These bits enable or disable
0
to IRQ interrupts are disabled
5 0
to IRQ interrupts are enabled
5 0
4 3
IRQ4E IRQ3E
0 0
R/W R/W
IRQ to IRQ enable
5 0
These bits enable or disable IRQ to IRQ interrupts
to IRQ interrupt requests.
0 5
2 1
IRQ2E IRQ1E IRQ0E
0 0
R/W R/W R/W
5 0
(Initial value)
0
0
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