Irq Enable Register (Ier) - Hitachi H8S/2678 Series Reference Manual

As shown in table 3.4, multiple interrupts are assigned to one IPR. Setting a value in the range
from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of
the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the
highest priority level, level 7, by setting H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority
levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt
mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if
the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to
the CPU.
3.3.3

IRQ Enable Register (IER)

Bit 15
IRQ15E
Initial value 0
Read/Write R/W
Bit 7
IRQ7E
Initial value 0
Read/Write R/W
IER is a 16-bit readable/writable register that controls enabling and disabling of interrupt requests
IRQ15 to IRQ0.
IER is initialized to H'0000 by a reset and in hardware standby mode.
Bits 15 to 0—IRQ15 to IRQ0 Enable (IRQ15E to IRQ0E): These bits select whether interrupts
IRQ15 to IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0 IRQn interrupts disabled
1 IRQn interrupts enabled
60
14 13
IRQ14E IRQ13E
0 0
R/W R/W
6 5
IRQ6E IRQ5E
0 0
R/W R/W
12 11
IRQ12E IRQ11E
0 0
R/W R/W
4 3
IRQ4E IRQ3E
0 0
R/W R/W
10 9
IRQ10E IRQ9E
0 0
R/W R/W
2 1
IRQ2E IRQ1E
0 0
R/W R/W
(Initial value)
(n = 15 to 0)
8
IRQ8E
0
R/W
0
IRQ0E
0
R/W