Interrupt Enable Register 1(Ienr1) - Hitachi H8/3672 Series Hardware Manual

3.2.3

Interrupt Enable Register 1(IENR1)

IENR1 enables direct transition interrupts, and external pin interrupts.
Bit Bit Name Initial Value
7 IENDT 0
−
6 0
5 IENWP 0
−
4 1
3 IEN3 0
−
2 0
−
1 0
0 IEN0 0
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked(I=1). If the above clear
operations are performed while I=0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
R/W Description
R/W Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt requests
are enabled.
−
Reserved
This bit is always read as 0, and cannot be modified.
R/W Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
−
Reserved
This bit is always read as 1, and cannot be modified.
R/W IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3 pin
are enabled.
−
Reserved
This bit is always read as 0, and cannot be modified.
−
Reserved
This bit is always read as 0, and cannot be modified.
R/W IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0 pin
are enabled.
Rev. 1.0, 03/01, page 45 of 280