Dma Write Enable Register (Dmawer); Figure 7.2 Areas For Register Re-Setting By Dtc (Example: Channel 0A) - Hitachi H8S/2215 Series Hardware Manual

7.3.6

DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions
so that only specific bits of DMACR for the specific channel and also DMABCR can be changed
to prevent inadvertent changes being made to registers other than those for the channel concerned.
The restrictions applied by DMAWER are valid for the DTC.
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end
interrupt, and reactivating channel 0A. The address register and count register area is re-set by the
first DTC transfer, then the control register area is re-set by the second DTC chain transfer.
When re-setting the control register area, perform masking by setting bits in DMAWER to prevent
modification of the contents of the other channels.

Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)

DMAWER controls enabling or disabling of writes to the DMACR and DMABCR by the DTC.
First transfer area
DTC
Second transfer area
using chain transfer
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
DMAWER DMATCR
DMACR0A DMACR0B
DMACR1A DMACR1B
DMABCR
Rev. 3.0, 10/02, page 161 of 686