Input Capture Register (Icr); Timer Interrupt Enable Register (Tier) - Hitachi SH7095 Hardware User Manual

11.2.3

Input Capture Register (ICR)

Bit:
Bit name:
Initial value:
R/W:
The ICR is a 16-bit read-only register. When a rising edge or falling edge of the input capture
signal is detected, the current FRC value is sent to ICR. At the same time, the input capture flag
(ICF) of FTCSR is set to 1. The edge of the input signal can be selected using the input edge select
bit (IEDGA) of TCR.
Because the ICR is a 16-bit register, data transfers involving the CPU go through a temporary
register (TEMP). See Section 11.3, CPU Interface, for more detailed information. To ensure that
the input capture operation is reliably performed, set the pulse width of the input capture input
signal to six system clocks (φ) or more.
The ICR is initialized to H'0000 by a reset, in the standby mode, and when the module standby
function is used.
11.2.4

Timer Interrupt Enable Register (TIER)

Bit:
Bit name:
Initial value:
R/W:
The TIER is an 8-bit read/write register that controls enabling of all interrupt requests. TIER is
initialized to H'01 by a reset, in the standby mode, and when the module standby function is used.
• Bit 7: Input capture interrupt enable (ICIE). Selects enable/disable for interrupts by the ICF
(ICI) when the input capture flag (ICF) of the FTCSR is set to 1.
Bit 7: ICIE
0
1
15 14
0 0
R R
7 6
ICIE —
0 0
R/W —
Description
Disables interrupt requests (ICI) from the ICF (initial value)
Enables interrupt requests (ICI) from the ICF
13 ...
...
0 ...
R ...
5 4
— — OCIAE
0 0
— — R/W
3 2
0 0
R R
3 2
OCIBE OVIE
0 0
R/W R/W
1 0
0 0
R R
1 0
—
0 1
—
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