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The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh
cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin.
(UCAS /LCAS)
Read access
(UCAS /LCAS)
Write access
Note: n = 2 to 5
Figure 6.18 Example of Wait State Insertion Timing (CSEL = 0)
Byte Access Control and CAS Output Pin
6.5.9
When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column
address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external
data bus are output. In the case of × 16-bit organization DRAM, the 2-CAS type can be
connected.
Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the
selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and
corresponding output pin selections.
150
T
φ
A
to A
23
0
AS
CSn(RAS)
PB4 /PB5
RD(WE)
D
to D
15
0
PB4 /PB5
RD(WE)
D
to D
15
0
Tr
Trw
T
p
c1
Row
High
High
Tw
Tw
T
c2
Column
Read data
Write data
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