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4.5.11
Byte Access Control
When DRAM with a ×16 configuration is connected, the 2-CAS access method is used for the
control signals needed for byte access.
Figure 4.27 shows the control timing for 2-CAS access, and figure 4.28 shows an example of 2-
CAS DRAM connection.
ø
Address bus
RASn (CSn)
UCAS
LCAS
WE (HWR)
OE (RD)
Upper data bus
Lower data bus
Note: n = 2 to 5
T
p
Row address
Figure 4.27 2-CAS Control Timing
(Upper Byte Write Access: RAST = 0, CAST = 0)
T
T
r
c1
Column address
High
High
T
c2
Write data
High-Z
149
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