Address Control Register (Adrcr) - Hitachi H8/3035 Series Hardware Manual

6.2.4 Address Control Register (ADRCR)

ADRCR is an 8-bit readable/writable register that enables address output on bus lines A
Bit
A
Initial value
Mode
1,3
Read/Write
Initial value
Mode
2
Read/Write
Address 23 to 21 enable
These bits enable PA
PA
A
ADRCR is initialized to H'FE in modes 1 and 3, and to H'FE in mode 2 by a reset and in
hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A
Writing 0 in this bit enables A
be modified and PA has its ordinary input/output functions.
4
Bit 7
A E Description
23
0 PA4 is the A23 address output pin
1 PA4 is the PA4/TP4/TIOCA1 input/output pin
Bit 6—Address 22 Enable (A
Writing 0 in this bit enables A
be modified and PA has its ordinary input/output functions.
5
Bit 6
A E Description
22
0 PA5 is the A22 address output pin
1 PA5 is the PA5/TP5/TIOCB1 input/output pin
102
7 6 5
E A E A E
23 22 21
1 1 1
— — —
1 1 1
R/W R/W R/W
to
6
to be used for A to
4 23
address output
21
E): Enables PA
23
address output from PA
23
E): Enables PA
22
address output from PA
22
4 3
— —
1 1
— —
1 1
— —
Reserved bits
to be used as the A address output pin.
4 23
. In modes other than 2 this bit cannot
4
to be used as the A address output pin.
5 22
. In modes other than 2 this bit cannot
5
to A
23 21
2 1 0
— — —
1 1 0
— — R/W
1 1 0
— — —
(Initial value)
(Initial value)
.