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DMA read
φ
Address bus
*
Bus release
Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the
bus is released one bus cycle is inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Full Address Mode (Burst Mode): Figure 7.18 shows a transfer example in which TEND
is enabled and word-size full address mode transfer (burst mode) is performed from external 16-
bit, 2-state access space to external 16-bit, 2-state access space.
φ
Address bus
*
Bus release
Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the
transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle
is inserted after the DMA write cycle.
DMA write
DMA read
Bus release
DMA read
DMA write DMA read DMA write DMA read DMA write
DMA write
DMA read DMA write
Bus release
Last transfer cycle
Burst transfer
Rev. 3.0, 10/02, page 183 of 686
DMA
dead
Last transfer cycle
Bus release
DMA
dead
Bus release
output
*
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