Edge Port Flag Register (Epfr) - Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Reference Manual

Edge Port Module (EPORT)
16.4.6

Edge Port Flag Register (EPFR)

The EPORT flag register (EPFR) individually latches EPORT edge events.
IPSBAR 0x13_0006 (EPFR)
Offset:
7
R
EPF7
W
Reset: 0
Field
7–1 Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR
EPFn indicates that the selected edge has been detected. Reset clears EPF7–EPF1.
Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until
cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn equals 00), pin
transitions do not affect this register.
0 Selected edge for IRQn pin has not been detected.
1 Selected edge for IRQn pin has been detected.
0 Reserved, must be cleared.
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
16-6
6 5
EPF6 EPF5 EPF4
0 0
Figure 16-7. EPORT Port Flag Register (EPFR)
Table 16-8. EPFR Field Descriptions
4 3
EPF3 EPF2
0 0
Description
Access: User read/write
2 1 0
0
EPF1
0 0 0
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