Target Abort; Latrule Disable; Communication Subsystem Initiator Interface - Freescale Semiconductor MCF5480 Reference Manual

Table 19-54. Non-Contiguous PCI to XL Bus Transfers (Requires Two XL Bus Accesses) (Continued)
PCI Bus
BE[3:
AD[2:0] 31:24 23:16
0]
0110 000 OP3
0110 100 OP3
0101 000 OP3
0101 100 OP3
0010 000 OP3
0010 100 OP3
0100 000 OP3
0100 100 OP3

19.4.5.4 Target Abort

A target abort will occur if the PCI address falls within a base address window (BAR0 or BAR1) that has
not been enabled. See Section 19.3.2.2, "Target Base Address Translation Register 0 (PCITBATR0),"
Section 19.3.2.3, "Target Base Address Translation Register 1 (PCITBATR1)."

19.4.5.5 Latrule Disable

The latrule disable bit in the interface control register,
(PCITCR)," prevents the PCI controller from automatically disconnecting a target transaction due to the
PCI 16/8 clock rule. With this bit set, it is possible to hang the PCI bus if the internal bus does not complete
the data transfer.
19.4.6

Communication Subsystem Initiator Interface

This interface provides for high-speed, autonomous DMA transactions to PCI with the PCI controller
operating as a standard communication subsystem peripheral. Full duplex operation is supported and direct
XL bus transactions can also be interleaved while comm bus transactions are in progress. Internal
arbitration will occur continuously to support transaction interleaving.
Arbitration") Multichannel DMA operation operates independently of the XL bus. Non-PCI transactions
19-66
15:8 7:0 A[29:31]
OP2 000
011
OP2 100
111
OP2 001
011
OP2 101
111
OP2 OP1 000
010
OP2 OP1 100
110
OP2 OP1 000
011
OP2 OP1 100
111
MCF548x Reference Manual, Rev. 3
XL Bus
Data Bus Byte Lanes
0 1 2 3
OP2
OP3
OP2
OP3
OP1
OP2 OP3
OP1 OP2
OP3
Section 19.3.2.4, "Target Control Register
4 5 6 7
OP2
OP3
OP2
OP3
OP1
OP2 OP3
OP1 OP2
OP3
(Section 19.4.2, "Initiator
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