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26.2.5 Controller Registers
The controller uses the following registers and structures:
Master Control Register (MCR). This register allows the user to impose a real-time
priority level on the internal arbiter for the controller bus access, to generate a software
reset using a write to this register, and set the EU and bus priority counts for Channels 3
and 4. For details on this register and its programming model, see Section 26.5.4.1,
Master Control Register (MCR), on page 26-77.
Controller Identification Register (CIR). This register provides an ID for the SEC used by
software to verify the supported security revision levels. It is a duplicate of the
information in the Controller IP Block Revision. For details on this register, see Section
26.5.4.2, Controller Identification Register (CIDR), on page 26-79.
Controller IP Block Revision Register (CIPBRR). This register contains a 64-bit value
that identifies the version of the SEC 2.1 protocol supported by this device. For details on
this register, see Section 26.5.4.3, Controller IP Block Revision Register (CIPBRR), on
page 26-79.
Controller EU Assignment Status Register (CEUASR). This register records the
assignment for each EU to a channel. If the EU is assigned a channel, it becomes
inaccessible to any other channel. For details on this register, see Section 26.5.4.4, EU
Assignment Status (EUASR), on page 26-80.
Controller Interrupt Enable Register (CIER). The CIER allows the user to enable or
disable interrupt generation by specific sources. After reset, all sources are disabled. When
a source is enabled by setting the corresponding bit in the CIER, it can set a bit in the
Interrupt Status Register (ISR) which generates an interrupt to the core processor. For
normal operation, enable all the channel interrupts and disable all the EU-specific
interrupts. The channels generate the appropriate interrupts to the core processor. For
details on this register, see Section 26.5.4.5, Controller Interrupt Enable Register (CIER),
on page 26-81.
Controller Interrupt Status Register (CISR). The ISR contains fields representing all
possible sources of interrupts. The Interrupt Status Register is cleared either by a reset, or
by writing the appropriate bits active in the Interrupt Clear Register. For details on this
register, see Section 26.5.4.6, Controller Interrupt Status Register (CISR), on page 26-84.
Controller Interrupt Clear Register (CICR). The CICR provides a means clear the CISR.
Writing a 1 to a bit in the CICR clears the corresponding bit in the ISR. If no other
interrupt is pending, it also deasserts the interrupt output pin IRQ. If the input source to the
ISR remains active, the appropriate ISR bit sets the IRQ is reasserted shortly thereafter.
The ICR bit clears automatically clear one cycle after it is written. For details on this
register, see Section 26.5.4.7, Controller Interrupt Clear Register (CICR), on page 26-87.
Freescale Semiconductor
MSC8144E Reference Manual, Rev. 3
SEC Controller
26-19
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