ST STM32G0 1 Series Reference Manual page 1202

FD controller area network (FDCAN)
Software initialization
Software initialization is started by setting INIT bit in FDCAN_CCCR register, either by
software or by a hardware reset, or by going Bus_Off. While INIT bit in FDCAN_CCCR
register is set, message transfer from and to the CAN bus is stopped, the status of the CAN
bus output FDCAN_TX is recessive (high). The counters of the Error Management Logic
(EML) are unchanged. Setting INIT bit in FDCAN_CCCR does not change any configuration
register. Clearing INIT bit in FDCAN_CCCR finishes the software initialization. Afterwards
the Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by
waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus_Idle) before
it can take part in bus activities and start the message transfer.
Access to the FDCAN configuration registers is only enabled when both INIT bit in
FDCAN_CCCR register and CCE bit in FDCAN_CCCR register are set.
CCE bit in FDCAN_CCCR register can only be set/cleared while INIT bit in FDCAN_CCCR
is set. CCE bit in FDCAN_CCCR register is automatically cleared when INIT bit in
FDCAN_CCCR is cleared.
The following registers are reset when CCE bit in FDCAN_CCCR register is set:
•
FDCAN_HPMS - High Priority Message Status
•
FDCAN_RXF0S - Rx FIFO 0 Status
•
FDCAN_RXF1S - Rx FIFO 1 Status
•
FDCAN_TXFQS - Tx FIFO/Queue Status
•
FDCAN_TXBRP - Tx Buffer Request Pending
•
FDCAN_TXBTO - Tx Buffer Transmission Occurred
•
FDCAN_TXBCF - Tx Buffer Cancellation Finished
• FDCAN_TXEFS - Tx Event FIFO Status
The Timeout Counter value TOC bit in FDCAN_TOCV register is preset to the value
configured by TOP bit in FDCAN_TOCC register when CCE bit in FDCAN_CCCR is set.
In addition the state machines of the Tx Handler and Rx Handler are held in idle state while
CCE bit in FDCAN_CCCR is set.
The following registers can be written only when CCE bit in FDCAN_CCCR register is
cleared:
•
TXBAR - Tx Buffer Add Request
• TXBCR - Tx Buffer Cancellation Request
TEST bit in FDCAN_CCCR and MON bit in FDCAN_CCCR can only be set by software
while both INIT bit in CCCR and CCE bit in CCCR register are set. Both bits may be reset at
any time. DAR bit in FDCAN_CCCR can only be set/cleared while both INIT bit in
FDCAN_CCCR and CCE bit in FDCAN_CCCR are set.
Normal operation
The FDCAN default operating mode after hardware reset is event-driven CAN
communication. TT Operation Mode is not supported.
Once the FDCAN is initialized and INIT bit in FDCAN_CCCR register is cleared, the FDCAN
synchronizes itself to the CAN bus and is ready for communication.
After passing the acceptance filtering, received messages including Message ID and DLC
are stored into the Rx FIFO 0 or Rx FIFO 1.
1202/1390 RM0444 Rev 5
RM0444