ST STM32G0 1 Series Reference Manual page 1205

RM0444
delay is greater than TSEG1 (time segment before sample point), a bit error is detected.
Without transceiver delay compensation, the bit rate in the data phase of a FDCAN frame is
limited by the transceivers loop delay.
The FDCAN implements a delay compensation mechanism to compensate the CAN
transceiver loop delay, thereby enabling transmission with higher bit rates during the
FDCAN data phase independent of the delay of a specific CAN transceiver.
To check for bit errors during the data phase of transmitting nodes, the delayed transmit
data is compared against the received data at the Secondary Sample Point SSP. If a bit
error is detected, the transmitter reacts on this bit error at the next following regular sample
point. During arbitration phase the delay compensation is always disabled.
The transmitter delay compensation enables configurations where the data bit time is
shorter than the transmitter delay, it is described in detail in the new ISO11898-1. It is
enabled by setting bit DBTP.TDC.
The received bit is compared against the transmitted bit at the SSP. The SSP position is
defined as the sum of the measured delay from the FDCAN transmit output pin FDCAN_TX
through the transceiver to the receive input pin FDCAN_RX plus the transmitter delay
compensation offset as configured by TDCR.TDCO. The transmitter delay compensation
offset is used to adjust the position of the SSP inside the received bit (e.g. half of the bit time
in the data phase). The position of the secondary sample point is rounded down to the next
integer number of mtq (minimum time quantum, that is one period of fdcan_tq_ck clock).
PSR.TDCV shows the actual transmitter delay compensation value. PSR.TDCV is cleared
when CCCR.INIT is set and is updated at each transmission of an FD frame while
DBTP.TDC is set.
The following boundary conditions have to be considered for the transmitter delay
compensation implemented in the FDCAN:
•
The sum of the measured delay from FDCAN_Tx to FDCAN_Rx and the configured
transmitter delay compensation offset TDCR.TDCO has to be less than 6 bit times in
the data phase.
•
The sum of the measured delay from FDCAN_TX to FDCAN_RX and the configured
transmitter delay compensation offset TDCR.TDCO has to be less or equal 127 mtq. If
the sum exceeds this value, the maximum value (127 mtq) is used for transmitter delay
compensation.
•
The data phase ends at the sample point of the CRC delimiter, that stops checking
received bits at the SSPs
If transmitter delay compensation is enabled by programming DBTP.TDC = 1, the
measurement is started within each transmitted CAN FD frame at the falling edge of bit FDF
to bit res. The measurement is stopped when this edge is seen at the receive input pin
FDCAN_TX of the transmitter. The resolution of this measurement is one mtq.
FD controller area network (FDCAN)
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