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T
p
EXTAL
Address
RD
HWR
RAS
CAS, LCAS
Data bus
Figure 4-35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1)
4.8.2
Pin States in Idle Cycle
Table 4-8 shows the pin states in an idle cycle.
Table 4-8
Pin States in Idle Cycle
Pins
Pin State
A
to A
Contents of next bus cycle
23
0
D
to D
High impedance
15
0
CSn
High*
CAS
High
AS
High
RD
High
HWR
High
LWR
High
DACKn
High
Note: * Remains low in DRAM space RAS down mode or a refresh cycle.
106
DRAM space read
T
T
T
r
c1
c2
External read
T
T
T
1
1
2
DRAM space write
T
T
T
3
c1
c1
Idle cycle
T
c2
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